The present invention generally relates to test vectors, and more particularly to built-in self-test response analysis using two dimension vector space.
In order to test complex integrated circuits, test circuits are added to the integrated circuit. The concept of adding circuits to a circuit for purposes of testing is known as xe2x80x9cbuilt-in self-testxe2x80x9d or BIST.
In part BIST circuits may provide built-in access to circuits that would not otherwise be available on a bare or packaged die. In part BIST circuits may provide signals closer to actual operational signals than comparable automatic test equipment. In part BIST circuits may facilitate bypassing test steps using such automatic test equipment thereby reducing the need to purchase such automatic test equipment. In part BIST circuits may facilitate a hierarchical test strategy for more efficiently diagnosing problems. In any event, BIST circuits are added to an integrated circuit and thus consume semiconductor die area in addition to that consumed by the application circuitry.
Conventionally, BIST circuits added to an integrated circuit comprise a test pattern generator (such a read-only-memory with stored patterns, a counter, exclusive-OR (XOR) circuit trees, a linear feedback shift register (LFSR), and the like), a response analyzer (such as a comparator with store responses, an LFSR, and the like), and a control block (such as a test manager or test controller circuit configured to activate a test and process responses from the response analyzer). A test vector is generated by a test pattern generator and provided to an application circuit of the integrated circuit. A test vector output is provided from the application circuit in response to the test vector input. Thus, an input test vector corresponding to a specific address, and an output test vector represents test data associated with a response of the application circuit to the input test vector. This test vector output is provided to a response analyzer for providing an output indicating whether the application circuit functioned as intended.
In xe2x80x9cA Tutorial on Built-In Self-Testxe2x80x94Part 2: Applicationsxe2x80x9d by Vishwani D. Agrawal, Charles R. Kime and Kewal K. Saluja in IEEE Journal of Design and Test of Computers, June 1993, pages 69-77, several configurations of BIST circuitry are disclosed divided into two groups, namely, test-per-clock and test-per-scan. In a test-per-clock configuration, for each clock period a test vector is applied and a test vector output is obtained in response to the test vector applied. In a test-per-scan configuration, a scan capability is used to apply a test vector and capture a response thereto each scan cycle, where a scan cycle is a number of clock cycles needed for shifting a vector into a serial scan path or to shift a response to such a vector out of such a serial scan path. In a test-per-clock period configuration using a multiple-input signature register or MISR (pronounced xe2x80x9cmiserxe2x80x9d) for a response analyzer, it is stated that XORs are needed on each output stage in addition to LFSR hardware. In one test-per-scan configuration using a MISR, a scan register output is used to drive a MISR on only a portion of outputs from a circuit under test (CUT), where remaining outputs are shifted from a scan register to such a MISR on each clock cycle. In another test-per-scan configuration known as STUMPS or xe2x80x9cself-test using an MISR and parallel shift register sequence generator,xe2x80x9d a MISR receives outputs from serial scan paths in parallel.
Heretofore, response analyzers have been at least equal, if not greater, in vector length or input width to their test pattern generator counter parts. For example, a MISR used for a response analyzer would be at least equal in input width to an LFSR used for generating an input vector. To reduce die area consumption, a MISR was integrated with an application circuit data shift register. By reuse of a data shift register as a test vector shift register, as opposed to using independent shift registers for data and test vector shifting, semiconductor die area consumption was reduced. Integration conventionally doubled shift register area consumption; however, using independent shift registers for data and test vectors would consume more area than an integrated configuration. In such integrated MISR and data shift register systems, a one-dimensional vector space is used for compression. In operational terms, each compression step is performed on a vector column-by-column basis in the MISR and then a compressed vector is outputted via the data shift register.
Accordingly, it would be desirable to provide a response analyzer that consumes less semiconductor die area than those of the past.
An aspect of the present invention is a response analyzer. More particularly, a shift register is configured to receive a plurality of inputs representing test data and to provide a plurality of outputs fewer in number than the plurality of inputs. A multiple-input signature register is configured to receive the plurality of outputs and to compress the plurality of outputs to an output.
Another aspect of the present invention is a method for compression of a vector. More particularly, a shift register is provided. A multiple-input signature register is coupled to the shift register. Bits of the vector are shifted out with the shift register to provide an output width less than the vector length. The bits are shifted out to the multiple-input signature register. The vector is compressed with the multiple-input signature register to produce an output.
Another aspect of the present invention is a response analyzer having a first stage configured to receive an input test vector and to provide said input test vector a portion at a time, wherein said portion is narrower in bit input width than said input test vector length, and having a second stage configured to receive each said portion and to compress said input test vector to provide an output.
Another aspect of the present invention is a response analyzer for built-in self-test circuitry. More particularly, a first shift register is configured to receive each test data vector of a plurality of test data vectors and to output each said test data vector a portion at a time, wherein said portion has fewer bits in input width than each said test data vector length. A second shift register is configured to receive each said portion and to compress each said test data vector. The second shift register is configured with feedback.